realview-simple-atomic.py (9282:ac627fdc8991) realview-simple-atomic.py (9288:3d6da8559605)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 22 unchanged lines hidden (view full) ---

31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 22 unchanged lines hidden (view full) ---

31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39 hit_latency = '1ns'
40 response_latency = '1ns'
39 hit_latency = 2
40 response_latency = 2
41 block_size = 64
42 mshrs = 4
43 tgts_per_mshr = 8
44 is_top_level = True
45
46# ----------------------
47# Base L2 Cache
48# ----------------------
49
50class L2(BaseCache):
51 block_size = 64
41 block_size = 64
42 mshrs = 4
43 tgts_per_mshr = 8
44 is_top_level = True
45
46# ----------------------
47# Base L2 Cache
48# ----------------------
49
50class L2(BaseCache):
51 block_size = 64
52 hit_latency = '10ns'
53 response_latency = '10ns'
52 hit_latency = 20
53 response_latency = 20
54 mshrs = 92
55 tgts_per_mshr = 16
56 write_buffers = 8
57
58# ---------------------
59# I/O Cache
60# ---------------------
61class IOCache(BaseCache):
62 assoc = 8
63 block_size = 64
54 mshrs = 92
55 tgts_per_mshr = 16
56 write_buffers = 8
57
58# ---------------------
59# I/O Cache
60# ---------------------
61class IOCache(BaseCache):
62 assoc = 8
63 block_size = 64
64 hit_latency = '50ns'
65 response_latency = '50ns'
64 hit_latency = 50
65 response_latency = 50
66 mshrs = 20
67 size = '1kB'
68 tgts_per_mshr = 12
69 addr_ranges = [AddrRange(0, size='256MB')]
70 forward_snoops = False
71
72#cpu
73cpu = AtomicSimpleCPU(cpu_id=0)
74#the system
75system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
76
77system.cpu = cpu
78
79#create the iocache
66 mshrs = 20
67 size = '1kB'
68 tgts_per_mshr = 12
69 addr_ranges = [AddrRange(0, size='256MB')]
70 forward_snoops = False
71
72#cpu
73cpu = AtomicSimpleCPU(cpu_id=0)
74#the system
75system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
76
77system.cpu = cpu
78
79#create the iocache
80system.iocache = IOCache()
80system.iocache = IOCache(clock = '1GHz')
81system.iocache.cpu_side = system.iobus.master
82system.iocache.mem_side = system.membus.slave
83
84#connect up the cpu and caches
85cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
86 L1(size = '32kB', assoc = 4),
87 L2(size = '4MB', assoc = 8))
88# create the interrupt controller
89cpu.createInterruptController()
90# connect cpu and caches to the rest of the system
91cpu.connectAllPorts(system.membus)
92# set the cpu clock along with the caches and l1-l2 bus
93cpu.clock = '2GHz'
94
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97
81system.iocache.cpu_side = system.iobus.master
82system.iocache.mem_side = system.membus.slave
83
84#connect up the cpu and caches
85cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
86 L1(size = '32kB', assoc = 4),
87 L2(size = '4MB', assoc = 8))
88# create the interrupt controller
89cpu.createInterruptController()
90# connect cpu and caches to the rest of the system
91cpu.connectAllPorts(system.membus)
92# set the cpu clock along with the caches and l1-l2 bus
93cpu.clock = '2GHz'
94
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97