realview-simple-atomic.py (9263:066099902102) realview-simple-atomic.py (9282:ac627fdc8991)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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68 tgts_per_mshr = 12
69 addr_ranges = [AddrRange(0, size='256MB')]
70 forward_snoops = False
71
72#cpu
73cpu = AtomicSimpleCPU(cpu_id=0)
74#the system
75system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 59 unchanged lines hidden (view full) ---

68 tgts_per_mshr = 12
69 addr_ranges = [AddrRange(0, size='256MB')]
70 forward_snoops = False
71
72#cpu
73cpu = AtomicSimpleCPU(cpu_id=0)
74#the system
75system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
76
77system.cpu = cpu
78
79#create the iocache
76system.iocache = IOCache()
77system.iocache.cpu_side = system.iobus.master
78system.iocache.mem_side = system.membus.slave
79
80system.iocache = IOCache()
81system.iocache.cpu_side = system.iobus.master
82system.iocache.mem_side = system.membus.slave
83
80system.cpu = cpu
81#create the l1/l2 bus
82system.toL2Bus = CoherentBus()
83
84#connect up the l2 cache
85system.l2c = L2(size='4MB', assoc=8)
86system.l2c.cpu_side = system.toL2Bus.master
87system.l2c.mem_side = system.membus.slave
88
89#connect up the cpu and l1s
90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
91 L1(size = '32kB', assoc = 4))
84#connect up the cpu and caches
85cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
86 L1(size = '32kB', assoc = 4),
87 L2(size = '4MB', assoc = 8))
92# create the interrupt controller
93cpu.createInterruptController()
88# create the interrupt controller
89cpu.createInterruptController()
94# connect cpu level-1 caches to shared level-2 cache
95cpu.connectAllPorts(system.toL2Bus, system.membus)
90# connect cpu and caches to the rest of the system
91cpu.connectAllPorts(system.membus)
92# set the cpu clock along with the caches and l1-l2 bus
96cpu.clock = '2GHz'
97
98root = Root(full_system=True, system=system)
99m5.ticks.setGlobalFrequency('1THz')
100
93cpu.clock = '2GHz'
94
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97