| realview-simple-atomic.py (8883:c92153af04ac) | realview-simple-atomic.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 62 unchanged lines hidden (view full) --- 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.iocache = IOCache() 74system.iocache.cpu_side = system.iobus.master 75system.iocache.mem_side = system.membus.slave 76 77system.cpu = cpu 78#create the l1/l2 bus | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 62 unchanged lines hidden (view full) --- 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.iocache = IOCache() 74system.iocache.cpu_side = system.iobus.master 75system.iocache.mem_side = system.membus.slave 76 77system.cpu = cpu 78#create the l1/l2 bus |
| 79system.toL2Bus = Bus() | 79system.toL2Bus = CoherentBus() |
| 80 81#connect up the l2 cache 82system.l2c = L2(size='4MB', assoc=8) 83system.l2c.cpu_side = system.toL2Bus.master 84system.l2c.mem_side = system.membus.slave 85 86#connect up the cpu and l1s 87cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 88 L1(size = '32kB', assoc = 4)) 89# create the interrupt controller 90cpu.createInterruptController() 91# connect cpu level-1 caches to shared level-2 cache 92cpu.connectAllPorts(system.toL2Bus, system.membus) 93cpu.clock = '2GHz' 94 95root = Root(full_system=True, system=system) 96m5.ticks.setGlobalFrequency('1THz') 97 | 80 81#connect up the l2 cache 82system.l2c = L2(size='4MB', assoc=8) 83system.l2c.cpu_side = system.toL2Bus.master 84system.l2c.mem_side = system.membus.slave 85 86#connect up the cpu and l1s 87cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 88 L1(size = '32kB', assoc = 4)) 89# create the interrupt controller 90cpu.createInterruptController() 91# connect cpu level-1 caches to shared level-2 cache 92cpu.connectAllPorts(system.toL2Bus, system.membus) 93cpu.clock = '2GHz' 94 95root = Root(full_system=True, system=system) 96m5.ticks.setGlobalFrequency('1THz') 97 |