| realview-simple-atomic.py (8801:1a84c6a81299) | realview-simple-atomic.py (8839:eeb293859255) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 57 unchanged lines hidden (view full) --- 66 addr_range=AddrRange(0, size='256MB') 67 forward_snoops = False 68 69#cpu 70cpu = AtomicSimpleCPU(cpu_id=0) 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.iocache = IOCache() | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 57 unchanged lines hidden (view full) --- 66 addr_range=AddrRange(0, size='256MB') 67 forward_snoops = False 68 69#cpu 70cpu = AtomicSimpleCPU(cpu_id=0) 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.iocache = IOCache() |
| 74system.iocache.cpu_side = system.iobus.port 75system.iocache.mem_side = system.membus.port | 74system.iocache.cpu_side = system.iobus.master 75system.iocache.mem_side = system.membus.slave |
| 76 77system.cpu = cpu 78#create the l1/l2 bus 79system.toL2Bus = Bus() 80 81#connect up the l2 cache 82system.l2c = L2(size='4MB', assoc=8) | 76 77system.cpu = cpu 78#create the l1/l2 bus 79system.toL2Bus = Bus() 80 81#connect up the l2 cache 82system.l2c = L2(size='4MB', assoc=8) |
| 83system.l2c.cpu_side = system.toL2Bus.port 84system.l2c.mem_side = system.membus.port | 83system.l2c.cpu_side = system.toL2Bus.master 84system.l2c.mem_side = system.membus.slave |
| 85 86#connect up the cpu and l1s 87cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 88 L1(size = '32kB', assoc = 4)) 89# connect cpu level-1 caches to shared level-2 cache 90cpu.connectAllPorts(system.toL2Bus, system.membus) 91cpu.clock = '2GHz' 92 93root = Root(full_system=True, system=system) 94m5.ticks.setGlobalFrequency('1THz') 95 | 85 86#connect up the cpu and l1s 87cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 88 L1(size = '32kB', assoc = 4)) 89# connect cpu level-1 caches to shared level-2 cache 90cpu.connectAllPorts(system.toL2Bus, system.membus) 91cpu.clock = '2GHz' 92 93root = Root(full_system=True, system=system) 94m5.ticks.setGlobalFrequency('1THz') 95 |