realview-simple-atomic.py (8528:1f95c9a0bb2f) realview-simple-atomic.py (8713:2f1a3e335255)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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65 tgts_per_mshr = 12
66 addr_range=AddrRange(0, size='256MB')
67 forward_snoops = False
68
69#cpu
70cpu = AtomicSimpleCPU(cpu_id=0)
71#the system
72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 56 unchanged lines hidden (view full) ---

65 tgts_per_mshr = 12
66 addr_range=AddrRange(0, size='256MB')
67 forward_snoops = False
68
69#cpu
70cpu = AtomicSimpleCPU(cpu_id=0)
71#the system
72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
73system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
74system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
75system.iocache = IOCache()
76system.iocache.cpu_side = system.iobus.port
77system.iocache.mem_side = system.membus.port
78
79system.cpu = cpu
80#create the l1/l2 bus
81system.toL2Bus = Bus()
82

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73system.iocache = IOCache()
74system.iocache.cpu_side = system.iobus.port
75system.iocache.mem_side = system.membus.port
76
77system.cpu = cpu
78#create the l1/l2 bus
79system.toL2Bus = Bus()
80

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