| realview-simple-atomic.py (8134:b01a51ff05fa) | realview-simple-atomic.py (8528:1f95c9a0bb2f) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 49 unchanged lines hidden (view full) --- 58# --------------------- 59class IOCache(BaseCache): 60 assoc = 8 61 block_size = 64 62 latency = '50ns' 63 mshrs = 20 64 size = '1kB' 65 tgts_per_mshr = 12 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 49 unchanged lines hidden (view full) --- 58# --------------------- 59class IOCache(BaseCache): 60 assoc = 8 61 block_size = 64 62 latency = '50ns' 63 mshrs = 20 64 size = '1kB' 65 tgts_per_mshr = 12 |
| 66 addr_range=AddrRange(0, size='128MB') | 66 addr_range=AddrRange(0, size='256MB') |
| 67 forward_snoops = False 68 69#cpu 70cpu = AtomicSimpleCPU(cpu_id=0) 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] | 67 forward_snoops = False 68 69#cpu 70cpu = AtomicSimpleCPU(cpu_id=0) 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] |
| 74system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] | 74system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] |
| 75system.iocache = IOCache() 76system.iocache.cpu_side = system.iobus.port 77system.iocache.mem_side = system.membus.port 78 79system.cpu = cpu 80#create the l1/l2 bus 81system.toL2Bus = Bus() 82 --- 15 unchanged lines hidden --- | 75system.iocache = IOCache() 76system.iocache.cpu_side = system.iobus.port 77system.iocache.mem_side = system.membus.port 78 79system.cpu = cpu 80#create the l1/l2 bus 81system.toL2Bus = Bus() 82 --- 15 unchanged lines hidden --- |