| realview-simple-atomic.py (7735:a1a85250e897) | realview-simple-atomic.py (7876:189b9b258779) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.port 85system.l2c.mem_side = system.membus.port 86 87#connect up the cpu and l1s 88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 89 L1(size = '32kB', assoc = 4)) 90# connect cpu level-1 caches to shared level-2 cache | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.port 85system.l2c.mem_side = system.membus.port 86 87#connect up the cpu and l1s 88cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 89 L1(size = '32kB', assoc = 4)) 90# connect cpu level-1 caches to shared level-2 cache |
| 91cpu.connectMemPorts(system.toL2Bus) | 91cpu.connectAllPorts(system.toL2Bus, system.membus) |
| 92cpu.clock = '2GHz' 93 94root = Root(system=system) 95m5.ticks.setGlobalFrequency('1THz') 96 | 92cpu.clock = '2GHz' 93 94root = Root(system=system) 95m5.ticks.setGlobalFrequency('1THz') 96 |