1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32import FSConfig 33 34# -------------------- 35# Base L1 Cache 36# ==================== 37 38class L1(BaseCache):
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32import FSConfig 33 34# -------------------- 35# Base L1 Cache 36# ==================== 37 38class L1(BaseCache):
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39 latency = '1ns'
| 39 hit_latency = '1ns' 40 response_latency = '1ns'
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40 block_size = 64 41 mshrs = 4 42 tgts_per_mshr = 8 43 is_top_level = True 44 45# ---------------------- 46# Base L2 Cache 47# ---------------------- 48 49class L2(BaseCache): 50 block_size = 64
| 41 block_size = 64 42 mshrs = 4 43 tgts_per_mshr = 8 44 is_top_level = True 45 46# ---------------------- 47# Base L2 Cache 48# ---------------------- 49 50class L2(BaseCache): 51 block_size = 64
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51 latency = '10ns'
| 52 hit_latency = '10ns' 53 response_latency = '10ns'
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52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56# --------------------- 57# I/O Cache 58# --------------------- 59class IOCache(BaseCache): 60 assoc = 8 61 block_size = 64
| 54 mshrs = 92 55 tgts_per_mshr = 16 56 write_buffers = 8 57 58# --------------------- 59# I/O Cache 60# --------------------- 61class IOCache(BaseCache): 62 assoc = 8 63 block_size = 64
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62 latency = '50ns'
| 64 hit_latency = '50ns' 65 response_latency = '50ns'
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63 mshrs = 20 64 size = '1kB' 65 tgts_per_mshr = 12 66 addr_ranges = [AddrRange(0, size='256MB')] 67 forward_snoops = False 68 69#cpu 70cpu = AtomicSimpleCPU(cpu_id=0) 71#the system 72system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 73system.iocache = IOCache() 74system.iocache.cpu_side = system.iobus.master 75system.iocache.mem_side = system.membus.slave 76 77system.cpu = cpu 78#create the l1/l2 bus 79system.toL2Bus = CoherentBus() 80 81#connect up the l2 cache 82system.l2c = L2(size='4MB', assoc=8) 83system.l2c.cpu_side = system.toL2Bus.master 84system.l2c.mem_side = system.membus.slave 85 86#connect up the cpu and l1s 87cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 88 L1(size = '32kB', assoc = 4)) 89# create the interrupt controller 90cpu.createInterruptController() 91# connect cpu level-1 caches to shared level-2 cache 92cpu.connectAllPorts(system.toL2Bus, system.membus) 93cpu.clock = '2GHz' 94 95root = Root(full_system=True, system=system) 96m5.ticks.setGlobalFrequency('1THz') 97
| 66 mshrs = 20 67 size = '1kB' 68 tgts_per_mshr = 12 69 addr_ranges = [AddrRange(0, size='256MB')] 70 forward_snoops = False 71 72#cpu 73cpu = AtomicSimpleCPU(cpu_id=0) 74#the system 75system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) 76system.iocache = IOCache() 77system.iocache.cpu_side = system.iobus.master 78system.iocache.mem_side = system.membus.slave 79 80system.cpu = cpu 81#create the l1/l2 bus 82system.toL2Bus = CoherentBus() 83 84#connect up the l2 cache 85system.l2c = L2(size='4MB', assoc=8) 86system.l2c.cpu_side = system.toL2Bus.master 87system.l2c.mem_side = system.membus.slave 88 89#connect up the cpu and l1s 90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 91 L1(size = '32kB', assoc = 4)) 92# create the interrupt controller 93cpu.createInterruptController() 94# connect cpu level-1 caches to shared level-2 cache 95cpu.connectAllPorts(system.toL2Bus, system.membus) 96cpu.clock = '2GHz' 97 98root = Root(full_system=True, system=system) 99m5.ticks.setGlobalFrequency('1THz') 100
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