1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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31m5.util.addToPath('../configs/common')
32import FSConfig
33
34# --------------------
35# Base L1 Cache
36# ====================
37
38class L1(BaseCache):
39 latency = '1ns'
40 block_size = 64
41 mshrs = 4
42 tgts_per_mshr = 8
43 is_top_level = True
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50 block_size = 64
51 latency = '10ns'
52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
56# ---------------------
57# I/O Cache
58# ---------------------
59class IOCache(BaseCache):
60 assoc = 8
61 block_size = 64
62 latency = '50ns'
63 mshrs = 20
64 size = '1kB'
65 tgts_per_mshr = 12
66 addr_ranges = [AddrRange(0, size='256MB')]
67 forward_snoops = False
68
69#cpu
70cpu = AtomicSimpleCPU(cpu_id=0)

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