realview-simple-atomic-dual.py (9288:3d6da8559605) realview-simple-atomic-dual.py (9310:aa7bf10e822a)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Benchmarks import *
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 17 unchanged lines hidden (view full) ---

26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Benchmarks import *
34from Caches import *
34
35
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40 hit_latency = 2
41 response_latency = 2
42 block_size = 64
43 mshrs = 4
44 tgts_per_mshr = 8
45 is_top_level = True
46
47# ----------------------
48# Base L2 Cache
49# ----------------------
50
51class L2(BaseCache):
52 block_size = 64
53 hit_latency = 20
54 response_latency = 20
55 mshrs = 92
56 tgts_per_mshr = 16
57 write_buffers = 8
58
59# ---------------------
60# I/O Cache
61# ---------------------
62class IOCache(BaseCache):
63 assoc = 8
64 block_size = 64
65 hit_latency = 50
66 response_latency = 50
67 mshrs = 20
68 size = '1kB'
69 tgts_per_mshr = 12
70 addr_ranges = [AddrRange(0, size='256MB')]
71 forward_snoops = False
72
73#cpu
74cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
75#the system
76system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
36#cpu
37cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
38#the system
39system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
77system.iocache = IOCache(clock = '1GHz')
40system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
78system.iocache.cpu_side = system.iobus.master
79system.iocache.mem_side = system.membus.slave
80
81system.cpu = cpus
82#create the l1/l2 bus
83system.toL2Bus = CoherentBus(clock = '2GHz')
84
85#connect up the l2 cache

--- 18 unchanged lines hidden --- 		41system.iocache.cpu_side = system.iobus.master
42system.iocache.mem_side = system.membus.slave
43
44system.cpu = cpus
45#create the l1/l2 bus
46system.toL2Bus = CoherentBus(clock = '2GHz')
47
48#connect up the l2 cache

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