realview-simple-atomic-dual.py (8846:2eaf1809c6c6) | realview-simple-atomic-dual.py (8876:44f8e7bb7fdf) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.master 85system.l2c.mem_side = system.membus.slave 86 87#connect up the cpu and l1s 88for c in cpus: 89 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 90 L1(size = '32kB', assoc = 4)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.master 85system.l2c.mem_side = system.membus.slave 86 87#connect up the cpu and l1s 88for c in cpus: 89 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 90 L1(size = '32kB', assoc = 4)) |
91 # create the interrupt controller 92 c.createInterruptController() |
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91 # connect cpu level-1 caches to shared level-2 cache 92 c.connectAllPorts(system.toL2Bus, system.membus) 93 c.clock = '2GHz' 94 95 96root = Root(full_system=True, system=system) 97m5.ticks.setGlobalFrequency('1THz') 98 | 93 # connect cpu level-1 caches to shared level-2 cache 94 c.connectAllPorts(system.toL2Bus, system.membus) 95 c.clock = '2GHz' 96 97 98root = Root(full_system=True, system=system) 99m5.ticks.setGlobalFrequency('1THz') 100 |