1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 23 unchanged lines hidden (view full) --- 32import FSConfig 33from Benchmarks import * 34 35# -------------------- 36# Base L1 Cache 37# ==================== 38 39class L1(BaseCache): |
40 hit_latency = '1ns' 41 response_latency = '1ns' |
42 block_size = 64 43 mshrs = 4 44 tgts_per_mshr = 8 45 is_top_level = True 46 47# ---------------------- 48# Base L2 Cache 49# ---------------------- 50 51class L2(BaseCache): 52 block_size = 64 |
53 hit_latency = '10ns' 54 response_latency = '10ns' |
55 mshrs = 92 56 tgts_per_mshr = 16 57 write_buffers = 8 58 59# --------------------- 60# I/O Cache 61# --------------------- 62class IOCache(BaseCache): 63 assoc = 8 64 block_size = 64 |
65 hit_latency = '50ns' 66 response_latency = '50ns' |
67 mshrs = 20 68 size = '1kB' 69 tgts_per_mshr = 12 70 addr_ranges = [AddrRange(0, size='256MB')] 71 forward_snoops = False 72 73#cpu 74cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] --- 29 unchanged lines hidden --- |