realview-o3.py (8631:8c038d4cd210) realview-o3.py (8713:2f1a3e335255)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 61 unchanged lines hidden (view full) ---

70#cpu
71cpu = DerivO3CPU(cpu_id=0)
72#the system
73system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
74
75system.cpu = cpu
76#create the l1/l2 bus
77system.toL2Bus = Bus()
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 61 unchanged lines hidden (view full) ---

70#cpu
71cpu = DerivO3CPU(cpu_id=0)
72#the system
73system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
74
75system.cpu = cpu
76#create the l1/l2 bus
77system.toL2Bus = Bus()
78system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
79system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
80system.iocache = IOCache()
81system.iocache.cpu_side = system.iobus.port
82system.iocache.mem_side = system.membus.port
83
84
85#connect up the l2 cache
86system.l2c = L2(size='4MB', assoc=8)
87system.l2c.cpu_side = system.toL2Bus.port

--- 12 unchanged lines hidden --- 		78system.iocache = IOCache()
79system.iocache.cpu_side = system.iobus.port
80system.iocache.mem_side = system.membus.port
81
82
83#connect up the l2 cache
84system.l2c = L2(size='4MB', assoc=8)
85system.l2c.cpu_side = system.toL2Bus.port

--- 12 unchanged lines hidden ---