1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 62 unchanged lines hidden (view full) --- 71 forward_snoops = False 72 73#cpu 74cpu = DerivO3CPU(cpu_id=0) 75#the system 76system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 77 78system.cpu = cpu |
79 80#create the iocache |
81system.iocache = IOCache() 82system.iocache.cpu_side = system.iobus.master 83system.iocache.mem_side = system.membus.slave 84 |
85#connect up the cpu and caches 86cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 87 L1(size = '32kB', assoc = 4), 88 L2(size = '4MB', assoc = 8)) |
89# create the interrupt controller 90cpu.createInterruptController() |
91# connect cpu and caches to the rest of the system 92cpu.connectAllPorts(system.membus) 93# set the cpu clock along with the caches and l1-l2 bus |
94cpu.clock = '2GHz' 95 96root = Root(full_system=True, system=system) 97m5.ticks.setGlobalFrequency('1THz') 98 |