realview-o3-dual.py (9310:aa7bf10e822a) | realview-o3-dual.py (9315:2e00867b5001) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 41system.iocache.cpu_side = system.iobus.master 42system.iocache.mem_side = system.membus.slave 43 44system.cpu = cpus 45#create the l1/l2 bus 46system.toL2Bus = CoherentBus(clock = '2GHz') 47 48#connect up the l2 cache | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 41system.iocache.cpu_side = system.iobus.master 42system.iocache.mem_side = system.membus.slave 43 44system.cpu = cpus 45#create the l1/l2 bus 46system.toL2Bus = CoherentBus(clock = '2GHz') 47 48#connect up the l2 cache |
49system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) | 49system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) |
50system.l2c.cpu_side = system.toL2Bus.master 51system.l2c.mem_side = system.membus.slave 52 53#connect up the cpu and l1s 54for c in cpus: | 50system.l2c.cpu_side = system.toL2Bus.master 51system.l2c.mem_side = system.membus.slave 52 53#connect up the cpu and l1s 54for c in cpus: |
55 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 56 L1(size = '32kB', assoc = 4)) | 55 c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), 56 L1Cache(size = '32kB', assoc = 4)) |
57 # create the interrupt controller 58 c.createInterruptController() 59 # connect cpu level-1 caches to shared level-2 cache 60 c.connectAllPorts(system.toL2Bus, system.membus) 61 c.clock = '2GHz' 62 63 64root = Root(full_system=True, system=system) 65m5.ticks.setGlobalFrequency('1THz') 66 | 57 # create the interrupt controller 58 c.createInterruptController() 59 # connect cpu level-1 caches to shared level-2 cache 60 c.connectAllPorts(system.toL2Bus, system.membus) 61 c.clock = '2GHz' 62 63 64root = Root(full_system=True, system=system) 65m5.ticks.setGlobalFrequency('1THz') 66 |