realview-o3-dual.py (8801:1a84c6a81299) | realview-o3-dual.py (8833:2870638642bd) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 69 unchanged lines hidden (view full) --- 78system.cpu = cpus 79#create the l1/l2 bus 80system.toL2Bus = Bus() 81 82#connect up the l2 cache 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.port 85system.l2c.mem_side = system.membus.port | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 69 unchanged lines hidden (view full) --- 78system.cpu = cpus 79#create the l1/l2 bus 80system.toL2Bus = Bus() 81 82#connect up the l2 cache 83system.l2c = L2(size='4MB', assoc=8) 84system.l2c.cpu_side = system.toL2Bus.port 85system.l2c.mem_side = system.membus.port |
86system.l2c.num_cpus = 2 | |
87 88#connect up the cpu and l1s 89for c in cpus: 90 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 91 L1(size = '32kB', assoc = 4)) 92 # connect cpu level-1 caches to shared level-2 cache 93 c.connectAllPorts(system.toL2Bus, system.membus) 94 c.clock = '2GHz' 95 96 97root = Root(full_system=True, system=system) 98m5.ticks.setGlobalFrequency('1THz') 99 | 86 87#connect up the cpu and l1s 88for c in cpus: 89 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 90 L1(size = '32kB', assoc = 4)) 91 # connect cpu level-1 caches to shared level-2 cache 92 c.connectAllPorts(system.toL2Bus, system.membus) 93 c.clock = '2GHz' 94 95 96root = Root(full_system=True, system=system) 97m5.ticks.setGlobalFrequency('1THz') 98 |