realview-o3-checker.py (9282:ac627fdc8991) realview-o3-checker.py (9288:3d6da8559605)
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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41import FSConfig
42
43
44# --------------------
45# Base L1 Cache
46# ====================
47
48class L1(BaseCache):
1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 32 unchanged lines hidden (view full) ---

41import FSConfig
42
43
44# --------------------
45# Base L1 Cache
46# ====================
47
48class L1(BaseCache):
49 hit_latency = '1ns'
50 response_latency = '1ns'
49 hit_latency = 2
50 response_latency = 2
51 block_size = 64
52 mshrs = 4
53 tgts_per_mshr = 20
54 is_top_level = True
55
56# ----------------------
57# Base L2 Cache
58# ----------------------
59
60class L2(BaseCache):
61 block_size = 64
51 block_size = 64
52 mshrs = 4
53 tgts_per_mshr = 20
54 is_top_level = True
55
56# ----------------------
57# Base L2 Cache
58# ----------------------
59
60class L2(BaseCache):
61 block_size = 64
62 hit_latency = '10ns'
63 response_latency = '10ns'
62 hit_latency = 20
63 response_latency = 20
64 mshrs = 92
65 tgts_per_mshr = 16
66 write_buffers = 8
67
68# ---------------------
69# I/O Cache
70# ---------------------
71class IOCache(BaseCache):
72 assoc = 8
73 block_size = 64
64 mshrs = 92
65 tgts_per_mshr = 16
66 write_buffers = 8
67
68# ---------------------
69# I/O Cache
70# ---------------------
71class IOCache(BaseCache):
72 assoc = 8
73 block_size = 64
74 hit_latency = '50ns'
75 response_latency = '50ns'
74 hit_latency = 50
75 response_latency = 50
76 mshrs = 20
77 size = '1kB'
78 tgts_per_mshr = 12
79 addr_ranges = [AddrRange(0, size='256MB')]
80 forward_snoops = False
81
82#cpu
83cpu = DerivO3CPU(cpu_id=0)
84#the system
85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
86
87system.cpu = cpu
88#connect up the checker
89cpu.addCheckerCpu()
90
91#create the iocache
76 mshrs = 20
77 size = '1kB'
78 tgts_per_mshr = 12
79 addr_ranges = [AddrRange(0, size='256MB')]
80 forward_snoops = False
81
82#cpu
83cpu = DerivO3CPU(cpu_id=0)
84#the system
85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
86
87system.cpu = cpu
88#connect up the checker
89cpu.addCheckerCpu()
90
91#create the iocache
92system.iocache = IOCache()
92system.iocache = IOCache(clock = '1GHz')
93system.iocache.cpu_side = system.iobus.master
94system.iocache.mem_side = system.membus.slave
95
96#connect up the cpu and caches
97cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
98 L1(size = '32kB', assoc = 4),
99 L2(size = '4MB', assoc = 8))
100# create the interrupt controller
101cpu.createInterruptController()
102# connect cpu and caches to the rest of the system
103cpu.connectAllPorts(system.membus)
104# set the cpu clock along with the caches and l1-l2 bus
105cpu.clock = '2GHz'
106
107root = Root(full_system=True, system=system)
108m5.ticks.setGlobalFrequency('1THz')
109
93system.iocache.cpu_side = system.iobus.master
94system.iocache.mem_side = system.membus.slave
95
96#connect up the cpu and caches
97cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
98 L1(size = '32kB', assoc = 4),
99 L2(size = '4MB', assoc = 8))
100# create the interrupt controller
101cpu.createInterruptController()
102# connect cpu and caches to the rest of the system
103cpu.connectAllPorts(system.membus)
104# set the cpu clock along with the caches and l1-l2 bus
105cpu.clock = '2GHz'
106
107root = Root(full_system=True, system=system)
108m5.ticks.setGlobalFrequency('1THz')
109