| realview-o3-checker.py (9263:066099902102) | realview-o3-checker.py (9282:ac627fdc8991) |
|---|---|
| 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 71 unchanged lines hidden (view full) --- 80 forward_snoops = False 81 82#cpu 83cpu = DerivO3CPU(cpu_id=0) 84#the system 85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 86 87system.cpu = cpu | 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 71 unchanged lines hidden (view full) --- 80 forward_snoops = False 81 82#cpu 83cpu = DerivO3CPU(cpu_id=0) 84#the system 85system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 86 87system.cpu = cpu |
| 88#create the l1/l2 bus 89system.toL2Bus = CoherentBus() | 88#connect up the checker 89cpu.addCheckerCpu() 90 91#create the iocache |
| 90system.iocache = IOCache() 91system.iocache.cpu_side = system.iobus.master 92system.iocache.mem_side = system.membus.slave 93 | 92system.iocache = IOCache() 93system.iocache.cpu_side = system.iobus.master 94system.iocache.mem_side = system.membus.slave 95 |
| 94 95#connect up the l2 cache 96system.l2c = L2(size='4MB', assoc=8) 97system.l2c.cpu_side = system.toL2Bus.master 98system.l2c.mem_side = system.membus.slave 99 100#connect up the checker 101cpu.addCheckerCpu() 102#connect up the cpu and l1s | 96#connect up the cpu and caches 97cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 98 L1(size = '32kB', assoc = 4), 99 L2(size = '4MB', assoc = 8)) 100# create the interrupt controller |
| 103cpu.createInterruptController() | 101cpu.createInterruptController() |
| 104cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 105 L1(size = '32kB', assoc = 4)) 106# connect cpu level-1 caches to shared level-2 cache 107cpu.connectAllPorts(system.toL2Bus, system.membus) | 102# connect cpu and caches to the rest of the system 103cpu.connectAllPorts(system.membus) 104# set the cpu clock along with the caches and l1-l2 bus |
| 108cpu.clock = '2GHz' 109 110root = Root(full_system=True, system=system) 111m5.ticks.setGlobalFrequency('1THz') 112 | 105cpu.clock = '2GHz' 106 107root = Root(full_system=True, system=system) 108m5.ticks.setGlobalFrequency('1THz') 109 |