| realview-o3-checker.py (8889:2e38fd9937a9) | realview-o3-checker.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 69 unchanged lines hidden (view full) --- 78 79#cpu 80cpu = DerivO3CPU(cpu_id=0) 81#the system 82system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 83 84system.cpu = cpu 85#create the l1/l2 bus | 1# Copyright (c) 2011 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 69 unchanged lines hidden (view full) --- 78 79#cpu 80cpu = DerivO3CPU(cpu_id=0) 81#the system 82system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False) 83 84system.cpu = cpu 85#create the l1/l2 bus |
| 86system.toL2Bus = Bus() | 86system.toL2Bus = CoherentBus() |
| 87system.iocache = IOCache() 88system.iocache.cpu_side = system.iobus.master 89system.iocache.mem_side = system.membus.slave 90 91 92#connect up the l2 cache 93system.l2c = L2(size='4MB', assoc=8) 94system.l2c.cpu_side = system.toL2Bus.master --- 15 unchanged lines hidden --- | 87system.iocache = IOCache() 88system.iocache.cpu_side = system.iobus.master 89system.iocache.mem_side = system.membus.slave 90 91 92#connect up the l2 cache 93system.l2c = L2(size='4MB', assoc=8) 94system.l2c.cpu_side = system.toL2Bus.master --- 15 unchanged lines hidden --- |