1# Copyright (c) 2011 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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41import FSConfig
42
43
44# --------------------
45# Base L1 Cache
46# ====================
47
48class L1(BaseCache):
49 latency = '1ns'
49 hit_latency = '1ns'
50 response_latency = '1ns'
51 block_size = 64
52 mshrs = 4
53 tgts_per_mshr = 20
54 is_top_level = True
55
56# ----------------------
57# Base L2 Cache
58# ----------------------
59
60class L2(BaseCache):
61 block_size = 64
61 latency = '10ns'
62 hit_latency = '10ns'
63 response_latency = '10ns'
64 mshrs = 92
65 tgts_per_mshr = 16
66 write_buffers = 8
67
68# ---------------------
69# I/O Cache
70# ---------------------
71class IOCache(BaseCache):
72 assoc = 8
73 block_size = 64
72 latency = '50ns'
74 hit_latency = '50ns'
75 response_latency = '50ns'
76 mshrs = 20
77 size = '1kB'
78 tgts_per_mshr = 12
79 addr_ranges = [AddrRange(0, size='256MB')]
80 forward_snoops = False
81
82#cpu
83cpu = DerivO3CPU(cpu_id=0)

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