pc-simple-timing.py (9282:ac627fdc8991) pc-simple-timing.py (9288:3d6da8559605)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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35
36mem_size = '128MB'
37
38# --------------------
39# Base L1 Cache
40# ====================
41
42class L1(BaseCache):
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 26 unchanged lines hidden (view full) ---

35
36mem_size = '128MB'
37
38# --------------------
39# Base L1 Cache
40# ====================
41
42class L1(BaseCache):
43 hit_latency = '1ns'
44 response_latency = '1ns'
43 hit_latency = 2
44 response_latency = 2
45 block_size = 64
46 mshrs = 4
47 tgts_per_mshr = 8
48 is_top_level = True
49
50# ----------------------
51# Base L2 Cache
52# ----------------------
53
54class L2(BaseCache):
55 block_size = 64
45 block_size = 64
46 mshrs = 4
47 tgts_per_mshr = 8
48 is_top_level = True
49
50# ----------------------
51# Base L2 Cache
52# ----------------------
53
54class L2(BaseCache):
55 block_size = 64
56 hit_latency = '10ns'
57 response_latency = '10ns'
56 hit_latency = 20
57 response_latency = 20
58 mshrs = 92
59 tgts_per_mshr = 16
60 write_buffers = 8
61
62# ---------------------
63# Page table walker cache
64# ---------------------
65class PageTableWalkerCache(BaseCache):
66 assoc = 2
67 block_size = 64
58 mshrs = 92
59 tgts_per_mshr = 16
60 write_buffers = 8
61
62# ---------------------
63# Page table walker cache
64# ---------------------
65class PageTableWalkerCache(BaseCache):
66 assoc = 2
67 block_size = 64
68 hit_latency = '1ns'
69 response_latency = '1ns'
68 hit_latency = 2
69 response_latency = 2
70 mshrs = 10
71 size = '1kB'
72 tgts_per_mshr = 12
73
74# ---------------------
75# I/O Cache
76# ---------------------
77class IOCache(BaseCache):
78 assoc = 8
79 block_size = 64
70 mshrs = 10
71 size = '1kB'
72 tgts_per_mshr = 12
73
74# ---------------------
75# I/O Cache
76# ---------------------
77class IOCache(BaseCache):
78 assoc = 8
79 block_size = 64
80 hit_latency = '50ns'
81 response_latency = '50ns'
80 hit_latency = 50
81 response_latency = 50
82 mshrs = 20
83 size = '1kB'
84 tgts_per_mshr = 12
85 addr_ranges = [AddrRange(0, size=mem_size)]
86 forward_snoops = False
87
88#cpu
89cpu = TimingSimpleCPU(cpu_id=0)
90#the system
91mdesc = SysConfig(disk = 'linux-x86.img')
92system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
93system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
94
95system.cpu = cpu
96
97#create the iocache
82 mshrs = 20
83 size = '1kB'
84 tgts_per_mshr = 12
85 addr_ranges = [AddrRange(0, size=mem_size)]
86 forward_snoops = False
87
88#cpu
89cpu = TimingSimpleCPU(cpu_id=0)
90#the system
91mdesc = SysConfig(disk = 'linux-x86.img')
92system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
93system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
94
95system.cpu = cpu
96
97#create the iocache
98system.iocache = IOCache()
98system.iocache = IOCache(clock = '1GHz')
99system.iocache.cpu_side = system.iobus.master
100system.iocache.mem_side = system.membus.slave
101
102#connect up the cpu and caches
103cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
104 L1(size = '32kB', assoc = 4),
105 L2(size = '4MB', assoc = 8),
106 PageTableWalkerCache(),
107 PageTableWalkerCache())
108# create the interrupt controller
109cpu.createInterruptController()
110# connect cpu and caches to the rest of the system
111cpu.connectAllPorts(system.membus)
112# set the cpu clock along with the caches and l1-l2 bus
113cpu.clock = '2GHz'
114
115root = Root(full_system=True, system=system)
116m5.ticks.setGlobalFrequency('1THz')
117
99system.iocache.cpu_side = system.iobus.master
100system.iocache.mem_side = system.membus.slave
101
102#connect up the cpu and caches
103cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
104 L1(size = '32kB', assoc = 4),
105 L2(size = '4MB', assoc = 8),
106 PageTableWalkerCache(),
107 PageTableWalkerCache())
108# create the interrupt controller
109cpu.createInterruptController()
110# connect cpu and caches to the rest of the system
111cpu.connectAllPorts(system.membus)
112# set the cpu clock along with the caches and l1-l2 bus
113cpu.clock = '2GHz'
114
115root = Root(full_system=True, system=system)
116m5.ticks.setGlobalFrequency('1THz')
117