pc-simple-timing.py (9263:066099902102) pc-simple-timing.py (9282:ac627fdc8991)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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88#cpu
89cpu = TimingSimpleCPU(cpu_id=0)
90#the system
91mdesc = SysConfig(disk = 'linux-x86.img')
92system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
93system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
94
95system.cpu = cpu
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 79 unchanged lines hidden (view full) ---

88#cpu
89cpu = TimingSimpleCPU(cpu_id=0)
90#the system
91mdesc = SysConfig(disk = 'linux-x86.img')
92system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
93system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
94
95system.cpu = cpu
96#create the l1/l2 bus
97system.toL2Bus = CoherentBus()
96
97#create the iocache
98system.iocache = IOCache()
99system.iocache.cpu_side = system.iobus.master
100system.iocache.mem_side = system.membus.slave
101
98system.iocache = IOCache()
99system.iocache.cpu_side = system.iobus.master
100system.iocache.mem_side = system.membus.slave
101
102
103#connect up the l2 cache
104system.l2c = L2(size='4MB', assoc=8)
105system.l2c.cpu_side = system.toL2Bus.master
106system.l2c.mem_side = system.membus.slave
107
108#connect up the cpu and l1s
109cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
110 L1(size = '32kB', assoc = 4),
111 PageTableWalkerCache(),
112 PageTableWalkerCache())
102#connect up the cpu and caches
103cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
104 L1(size = '32kB', assoc = 4),
105 L2(size = '4MB', assoc = 8),
106 PageTableWalkerCache(),
107 PageTableWalkerCache())
113# create the interrupt controller
114cpu.createInterruptController()
108# create the interrupt controller
109cpu.createInterruptController()
115# connect cpu level-1 caches to shared level-2 cache
116cpu.connectAllPorts(system.toL2Bus, system.membus)
110# connect cpu and caches to the rest of the system
111cpu.connectAllPorts(system.membus)
112# set the cpu clock along with the caches and l1-l2 bus
117cpu.clock = '2GHz'
118
119root = Root(full_system=True, system=system)
120m5.ticks.setGlobalFrequency('1THz')
121
113cpu.clock = '2GHz'
114
115root = Root(full_system=True, system=system)
116m5.ticks.setGlobalFrequency('1THz')
117