| pc-simple-timing.py (8883:c92153af04ac) | pc-simple-timing.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 76 unchanged lines hidden (view full) --- 85cpu = TimingSimpleCPU(cpu_id=0) 86#the system 87mdesc = SysConfig(disk = 'linux-x86.img') 88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc) 89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 90 91system.cpu = cpu 92#create the l1/l2 bus | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 76 unchanged lines hidden (view full) --- 85cpu = TimingSimpleCPU(cpu_id=0) 86#the system 87mdesc = SysConfig(disk = 'linux-x86.img') 88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc) 89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 90 91system.cpu = cpu 92#create the l1/l2 bus |
| 93system.toL2Bus = Bus() | 93system.toL2Bus = CoherentBus() |
| 94system.iocache = IOCache() 95system.iocache.cpu_side = system.iobus.master 96system.iocache.mem_side = system.membus.slave 97 98 99#connect up the l2 cache 100system.l2c = L2(size='4MB', assoc=8) 101system.l2c.cpu_side = system.toL2Bus.master --- 16 unchanged lines hidden --- | 94system.iocache = IOCache() 95system.iocache.cpu_side = system.iobus.master 96system.iocache.mem_side = system.membus.slave 97 98 99#connect up the l2 cache 100system.l2c = L2(size='4MB', assoc=8) 101system.l2c.cpu_side = system.toL2Bus.master --- 16 unchanged lines hidden --- |