pc-simple-timing.py (8839:eeb293859255) | pc-simple-timing.py (8876:44f8e7bb7fdf) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 92 unchanged lines hidden (view full) --- 101system.l2c.cpu_side = system.toL2Bus.master 102system.l2c.mem_side = system.membus.slave 103 104#connect up the cpu and l1s 105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 106 L1(size = '32kB', assoc = 4), 107 PageTableWalkerCache(), 108 PageTableWalkerCache()) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 92 unchanged lines hidden (view full) --- 101system.l2c.cpu_side = system.toL2Bus.master 102system.l2c.mem_side = system.membus.slave 103 104#connect up the cpu and l1s 105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 106 L1(size = '32kB', assoc = 4), 107 PageTableWalkerCache(), 108 PageTableWalkerCache()) |
109# create the interrupt controller 110cpu.createInterruptController() |
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109# connect cpu level-1 caches to shared level-2 cache 110cpu.connectAllPorts(system.toL2Bus, system.membus) 111cpu.clock = '2GHz' 112 113root = Root(full_system=True, system=system) 114m5.ticks.setGlobalFrequency('1THz') 115 | 111# connect cpu level-1 caches to shared level-2 cache 112cpu.connectAllPorts(system.toL2Bus, system.membus) 113cpu.clock = '2GHz' 114 115root = Root(full_system=True, system=system) 116m5.ticks.setGlobalFrequency('1THz') 117 |