pc-simple-timing.py (8801:1a84c6a81299) pc-simple-timing.py (8839:eeb293859255)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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87mdesc = SysConfig(disk = 'linux-x86.img')
88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
90
91system.cpu = cpu
92#create the l1/l2 bus
93system.toL2Bus = Bus()
94system.iocache = IOCache(addr_range=mem_size)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 78 unchanged lines hidden (view full) ---

87mdesc = SysConfig(disk = 'linux-x86.img')
88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
90
91system.cpu = cpu
92#create the l1/l2 bus
93system.toL2Bus = Bus()
94system.iocache = IOCache(addr_range=mem_size)
95system.iocache.cpu_side = system.iobus.port
96system.iocache.mem_side = system.membus.port
95system.iocache.cpu_side = system.iobus.master
96system.iocache.mem_side = system.membus.slave
97
98
99#connect up the l2 cache
100system.l2c = L2(size='4MB', assoc=8)
97
98
99#connect up the l2 cache
100system.l2c = L2(size='4MB', assoc=8)
101system.l2c.cpu_side = system.toL2Bus.port
102system.l2c.mem_side = system.membus.port
101system.l2c.cpu_side = system.toL2Bus.master
102system.l2c.mem_side = system.membus.slave
103
104#connect up the cpu and l1s
105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
106 L1(size = '32kB', assoc = 4),
107 PageTableWalkerCache(),
108 PageTableWalkerCache())
109# connect cpu level-1 caches to shared level-2 cache
110cpu.connectAllPorts(system.toL2Bus, system.membus)
111cpu.clock = '2GHz'
112
113root = Root(full_system=True, system=system)
114m5.ticks.setGlobalFrequency('1THz')
115
103
104#connect up the cpu and l1s
105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
106 L1(size = '32kB', assoc = 4),
107 PageTableWalkerCache(),
108 PageTableWalkerCache())
109# connect cpu level-1 caches to shared level-2 cache
110cpu.connectAllPorts(system.toL2Bus, system.membus)
111cpu.clock = '2GHz'
112
113root = Root(full_system=True, system=system)
114m5.ticks.setGlobalFrequency('1THz')
115