95,96c95,96
< system.iocache.cpu_side = system.iobus.port
< system.iocache.mem_side = system.membus.port
---
> system.iocache.cpu_side = system.iobus.master
> system.iocache.mem_side = system.membus.slave
101,102c101,102
< system.l2c.cpu_side = system.toL2Bus.port
< system.l2c.mem_side = system.membus.port
---
> system.l2c.cpu_side = system.toL2Bus.master
> system.l2c.mem_side = system.membus.slave