1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35
36mem_size = '128MB'
37
38# --------------------
39# Base L1 Cache
40# ====================
41
42class L1(BaseCache):
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Benchmarks import SysConfig
33import FSConfig
34
35
36mem_size = '128MB'
37
38# --------------------
39# Base L1 Cache
40# ====================
41
42class L1(BaseCache):
|
43 latency = '1ns'
| 43 hit_latency = '1ns'
44 response_latency = '1ns'
|
44 block_size = 64
45 mshrs = 4
46 tgts_per_mshr = 8
47 is_top_level = True
48
49# ----------------------
50# Base L2 Cache
51# ----------------------
52
53class L2(BaseCache):
54 block_size = 64
| 45 block_size = 64
46 mshrs = 4
47 tgts_per_mshr = 8
48 is_top_level = True
49
50# ----------------------
51# Base L2 Cache
52# ----------------------
53
54class L2(BaseCache):
55 block_size = 64
|
55 latency = '10ns'
| 56 hit_latency = '10ns'
57 response_latency = '10ns'
|
56 mshrs = 92
57 tgts_per_mshr = 16
58 write_buffers = 8
59
60# ---------------------
61# Page table walker cache
62# ---------------------
63class PageTableWalkerCache(BaseCache):
64 assoc = 2
65 block_size = 64
| 58 mshrs = 92
59 tgts_per_mshr = 16
60 write_buffers = 8
61
62# ---------------------
63# Page table walker cache
64# ---------------------
65class PageTableWalkerCache(BaseCache):
66 assoc = 2
67 block_size = 64
|
66 latency = '1ns'
| 68 hit_latency = '1ns'
69 response_latency = '1ns'
|
67 mshrs = 10
68 size = '1kB'
69 tgts_per_mshr = 12
70
71# ---------------------
72# I/O Cache
73# ---------------------
74class IOCache(BaseCache):
75 assoc = 8
76 block_size = 64
| 70 mshrs = 10
71 size = '1kB'
72 tgts_per_mshr = 12
73
74# ---------------------
75# I/O Cache
76# ---------------------
77class IOCache(BaseCache):
78 assoc = 8
79 block_size = 64
|
77 latency = '50ns'
| 80 hit_latency = '50ns'
81 response_latency = '50ns'
|
78 mshrs = 20
79 size = '1kB'
80 tgts_per_mshr = 12
81 addr_ranges = [AddrRange(0, size=mem_size)]
82 forward_snoops = False
83
84#cpu
85cpu = TimingSimpleCPU(cpu_id=0)
86#the system
87mdesc = SysConfig(disk = 'linux-x86.img')
88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
90
91system.cpu = cpu
92#create the l1/l2 bus
93system.toL2Bus = CoherentBus()
94system.iocache = IOCache()
95system.iocache.cpu_side = system.iobus.master
96system.iocache.mem_side = system.membus.slave
97
98
99#connect up the l2 cache
100system.l2c = L2(size='4MB', assoc=8)
101system.l2c.cpu_side = system.toL2Bus.master
102system.l2c.mem_side = system.membus.slave
103
104#connect up the cpu and l1s
105cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
106 L1(size = '32kB', assoc = 4),
107 PageTableWalkerCache(),
108 PageTableWalkerCache())
109# create the interrupt controller
110cpu.createInterruptController()
111# connect cpu level-1 caches to shared level-2 cache
112cpu.connectAllPorts(system.toL2Bus, system.membus)
113cpu.clock = '2GHz'
114
115root = Root(full_system=True, system=system)
116m5.ticks.setGlobalFrequency('1THz')
117
| 82 mshrs = 20
83 size = '1kB'
84 tgts_per_mshr = 12
85 addr_ranges = [AddrRange(0, size=mem_size)]
86 forward_snoops = False
87
88#cpu
89cpu = TimingSimpleCPU(cpu_id=0)
90#the system
91mdesc = SysConfig(disk = 'linux-x86.img')
92system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
93system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
94
95system.cpu = cpu
96#create the l1/l2 bus
97system.toL2Bus = CoherentBus()
98system.iocache = IOCache()
99system.iocache.cpu_side = system.iobus.master
100system.iocache.mem_side = system.membus.slave
101
102
103#connect up the l2 cache
104system.l2c = L2(size='4MB', assoc=8)
105system.l2c.cpu_side = system.toL2Bus.master
106system.l2c.mem_side = system.membus.slave
107
108#connect up the cpu and l1s
109cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
110 L1(size = '32kB', assoc = 4),
111 PageTableWalkerCache(),
112 PageTableWalkerCache())
113# create the interrupt controller
114cpu.createInterruptController()
115# connect cpu level-1 caches to shared level-2 cache
116cpu.connectAllPorts(system.toL2Bus, system.membus)
117cpu.clock = '2GHz'
118
119root = Root(full_system=True, system=system)
120m5.ticks.setGlobalFrequency('1THz')
121
|