pc-simple-timing.py (8876:44f8e7bb7fdf) | pc-simple-timing.py (8883:c92153af04ac) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 64 unchanged lines hidden (view full) --- 73# --------------------- 74class IOCache(BaseCache): 75 assoc = 8 76 block_size = 64 77 latency = '50ns' 78 mshrs = 20 79 size = '1kB' 80 tgts_per_mshr = 12 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 64 unchanged lines hidden (view full) --- 73# --------------------- 74class IOCache(BaseCache): 75 assoc = 8 76 block_size = 64 77 latency = '50ns' 78 mshrs = 20 79 size = '1kB' 80 tgts_per_mshr = 12 |
81 addr_range = AddrRange(0, size=mem_size) | 81 addr_ranges = [AddrRange(0, size=mem_size)] |
82 forward_snoops = False 83 84#cpu 85cpu = TimingSimpleCPU(cpu_id=0) 86#the system 87mdesc = SysConfig(disk = 'linux-x86.img') 88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc) 89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 90 91system.cpu = cpu 92#create the l1/l2 bus 93system.toL2Bus = Bus() | 82 forward_snoops = False 83 84#cpu 85cpu = TimingSimpleCPU(cpu_id=0) 86#the system 87mdesc = SysConfig(disk = 'linux-x86.img') 88system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc) 89system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 90 91system.cpu = cpu 92#create the l1/l2 bus 93system.toL2Bus = Bus() |
94system.iocache = IOCache(addr_range=mem_size) | 94system.iocache = IOCache() |
95system.iocache.cpu_side = system.iobus.master 96system.iocache.mem_side = system.membus.slave 97 98 99#connect up the l2 cache 100system.l2c = L2(size='4MB', assoc=8) 101system.l2c.cpu_side = system.toL2Bus.master 102system.l2c.mem_side = system.membus.slave --- 15 unchanged lines hidden --- | 95system.iocache.cpu_side = system.iobus.master 96system.iocache.mem_side = system.membus.slave 97 98 99#connect up the l2 cache 100system.l2c = L2(size='4MB', assoc=8) 101system.l2c.cpu_side = system.toL2Bus.master 102system.l2c.mem_side = system.membus.slave --- 15 unchanged lines hidden --- |