1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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35
36mem_size = '128MB'
37
38# --------------------
39# Base L1 Cache
40# ====================
41
42class L1(BaseCache):
43 hit_latency = '1ns'
44 response_latency = '1ns'
45 block_size = 64
46 mshrs = 4
47 tgts_per_mshr = 8
48 is_top_level = True
49
50# ----------------------
51# Base L2 Cache
52# ----------------------
53
54class L2(BaseCache):
55 block_size = 64
56 hit_latency = '10ns'
57 response_latency = '10ns'
58 mshrs = 92
59 tgts_per_mshr = 16
60 write_buffers = 8
61
62# ---------------------
63# Page table walker cache
64# ---------------------
65class PageTableWalkerCache(BaseCache):
66 assoc = 2
67 block_size = 64
68 hit_latency = '1ns'
69 response_latency = '1ns'
70 mshrs = 10
71 size = '1kB'
72 tgts_per_mshr = 12
73
74# ---------------------
75# I/O Cache
76# ---------------------
77class IOCache(BaseCache):
78 assoc = 8
79 block_size = 64
80 hit_latency = '50ns'
81 response_latency = '50ns'
82 mshrs = 20
83 size = '1kB'
84 tgts_per_mshr = 12
85 addr_ranges = [AddrRange(0, size=mem_size)]
86 forward_snoops = False
87
88#cpu
89cpu = TimingSimpleCPU(cpu_id=0)

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