pc-simple-atomic.py (9310:aa7bf10e822a) pc-simple-atomic.py (9315:2e00867b5001)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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45system.cpu = cpu
46
47#create the iocache
48system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
49system.iocache.cpu_side = system.iobus.master
50system.iocache.mem_side = system.membus.slave
51
52#connect up the cpu and caches
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 36 unchanged lines hidden (view full) ---

45system.cpu = cpu
46
47#create the iocache
48system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
49system.iocache.cpu_side = system.iobus.master
50system.iocache.mem_side = system.membus.slave
51
52#connect up the cpu and caches
53cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
54 L1(size = '32kB', assoc = 4),
55 L2(size = '4MB', assoc = 8),
53cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
54 L1Cache(size = '32kB', assoc = 4),
55 L2Cache(size = '4MB', assoc = 8),
56 PageTableWalkerCache(),
57 PageTableWalkerCache())
58# create the interrupt controller
59cpu.createInterruptController()
60# connect cpu and caches to the rest of the system
61cpu.connectAllPorts(system.membus)
62# set the cpu clock along with the caches and l1-l2 bus
63cpu.clock = '2GHz'
64
65root = Root(full_system=True, system=system)
66m5.ticks.setGlobalFrequency('1THz')
67
56 PageTableWalkerCache(),
57 PageTableWalkerCache())
58# create the interrupt controller
59cpu.createInterruptController()
60# connect cpu and caches to the rest of the system
61cpu.connectAllPorts(system.membus)
62# set the cpu clock along with the caches and l1-l2 bus
63cpu.clock = '2GHz'
64
65root = Root(full_system=True, system=system)
66m5.ticks.setGlobalFrequency('1THz')
67