pc-simple-atomic.py (9263:066099902102) pc-simple-atomic.py (9282:ac627fdc8991)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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87 is_top_level = True
88
89#cpu
90cpu = AtomicSimpleCPU(cpu_id=0)
91#the system
92mdesc = SysConfig(disk = 'linux-x86.img')
93system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
94system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 78 unchanged lines hidden (view full) ---

87 is_top_level = True
88
89#cpu
90cpu = AtomicSimpleCPU(cpu_id=0)
91#the system
92mdesc = SysConfig(disk = 'linux-x86.img')
93system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
94system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
95
96system.cpu = cpu
97
98#create the iocache
95system.iocache = IOCache()
96system.iocache.cpu_side = system.iobus.master
97system.iocache.mem_side = system.membus.slave
98
99system.iocache = IOCache()
100system.iocache.cpu_side = system.iobus.master
101system.iocache.mem_side = system.membus.slave
102
99system.cpu = cpu
100#create the l1/l2 bus
101system.toL2Bus = CoherentBus()
102
103#connect up the l2 cache
104system.l2c = L2(size='4MB', assoc=8)
105system.l2c.cpu_side = system.toL2Bus.master
106system.l2c.mem_side = system.membus.slave
107
108#connect up the cpu and l1s
109cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
110 L1(size = '32kB', assoc = 4),
111 PageTableWalkerCache(),
112 PageTableWalkerCache())
103#connect up the cpu and caches
104cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
105 L1(size = '32kB', assoc = 4),
106 L2(size = '4MB', assoc = 8),
107 PageTableWalkerCache(),
108 PageTableWalkerCache())
113# create the interrupt controller
114cpu.createInterruptController()
109# create the interrupt controller
110cpu.createInterruptController()
115# connect cpu level-1 caches to shared level-2 cache
116cpu.connectAllPorts(system.toL2Bus, system.membus)
111# connect cpu and caches to the rest of the system
112cpu.connectAllPorts(system.membus)
113# set the cpu clock along with the caches and l1-l2 bus
117cpu.clock = '2GHz'
118
119root = Root(full_system=True, system=system)
120m5.ticks.setGlobalFrequency('1THz')
121
114cpu.clock = '2GHz'
115
116root = Root(full_system=True, system=system)
117m5.ticks.setGlobalFrequency('1THz')
118