1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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34
35mem_size = '128MB'
36
37# --------------------
38# Base L1 Cache
39# ====================
40
41class L1(BaseCache):
42 latency = '1ns'
43 block_size = 64
44 mshrs = 4
45 tgts_per_mshr = 8
46 is_top_level = True
47
48# ----------------------
49# Base L2 Cache
50# ----------------------
51
52class L2(BaseCache):
53 block_size = 64
54 latency = '10ns'
55 mshrs = 92
56 tgts_per_mshr = 16
57 write_buffers = 8
58
59# ---------------------
60# Page table walker cache
61# ---------------------
62class PageTableWalkerCache(BaseCache):
63 assoc = 2
64 block_size = 64
65 latency = '1ns'
66 mshrs = 10
67 size = '1kB'
68 tgts_per_mshr = 12
69 is_top_level = True
70
71# ---------------------
72# I/O Cache
73# ---------------------
74class IOCache(BaseCache):
75 assoc = 8
76 block_size = 64
77 latency = '50ns'
78 mshrs = 20
79 size = '1kB'
80 tgts_per_mshr = 12
81 addr_ranges = [AddrRange(0, size=mem_size)]
82 forward_snoops = False
83 is_top_level = True
84
85#cpu

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