1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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34
35mem_size = '128MB'
36
37# --------------------
38# Base L1 Cache
39# ====================
40
41class L1(BaseCache):
42 hit_latency = '1ns'
43 response_latency = '1ns'
44 block_size = 64
45 mshrs = 4
46 tgts_per_mshr = 8
47 is_top_level = True
48
49# ----------------------
50# Base L2 Cache
51# ----------------------
52
53class L2(BaseCache):
54 block_size = 64
55 hit_latency = '10ns'
56 response_latency = '10ns'
57 mshrs = 92
58 tgts_per_mshr = 16
59 write_buffers = 8
60
61# ---------------------
62# Page table walker cache
63# ---------------------
64class PageTableWalkerCache(BaseCache):
65 assoc = 2
66 block_size = 64
67 hit_latency = '1ns'
68 response_latency = '1ns'
69 mshrs = 10
70 size = '1kB'
71 tgts_per_mshr = 12
72 is_top_level = True
73
74# ---------------------
75# I/O Cache
76# ---------------------
77class IOCache(BaseCache):
78 assoc = 8
79 block_size = 64
80 hit_latency = '50ns'
81 response_latency = '50ns'
82 mshrs = 20
83 size = '1kB'
84 tgts_per_mshr = 12
85 addr_ranges = [AddrRange(0, size=mem_size)]
86 forward_snoops = False
87 is_top_level = True
88
89#cpu

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