pc-o3-timing.py (9288:3d6da8559605) | pc-o3-timing.py (9310:aa7bf10e822a) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Benchmarks import SysConfig 33import FSConfig | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32from Benchmarks import SysConfig 33import FSConfig |
34from Caches import * |
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34 35mem_size = '128MB' 36 | 35 36mem_size = '128MB' 37 |
37# -------------------- 38# Base L1 Cache 39# ==================== 40 41class L1(BaseCache): 42 hit_latency = 2 43 response_latency = 2 44 block_size = 64 45 mshrs = 4 46 tgts_per_mshr = 20 47 is_top_level = True 48 49# ---------------------- 50# Base L2 Cache 51# ---------------------- 52 53class L2(BaseCache): 54 block_size = 64 55 hit_latency = 20 56 response_latency = 20 57 mshrs = 92 58 tgts_per_mshr = 16 59 write_buffers = 8 60 61# --------------------- 62# Page table walker cache 63# --------------------- 64class PageTableWalkerCache(BaseCache): 65 assoc = 2 66 block_size = 64 67 hit_latency = 2 68 response_latency = 2 69 mshrs = 10 70 size = '1kB' 71 tgts_per_mshr = 12 72 73# --------------------- 74# I/O Cache 75# --------------------- 76class IOCache(BaseCache): 77 assoc = 8 78 block_size = 64 79 hit_latency = 50 80 response_latency = 50 81 mshrs = 20 82 size = '1kB' 83 tgts_per_mshr = 12 84 addr_ranges = [AddrRange(0, size=mem_size)] 85 forward_snoops = False 86 | |
87#cpu 88cpu = DerivO3CPU(cpu_id=0) 89#the system 90mdesc = SysConfig(disk = 'linux-x86.img') 91system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 92system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 93 94system.cpu = cpu 95 96#create the iocache | 38#cpu 39cpu = DerivO3CPU(cpu_id=0) 40#the system 41mdesc = SysConfig(disk = 'linux-x86.img') 42system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 43system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') 44 45system.cpu = cpu 46 47#create the iocache |
97system.iocache = IOCache(clock = '1GHz') | 48system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) |
98system.iocache.cpu_side = system.iobus.master 99system.iocache.mem_side = system.membus.slave 100 101#connect up the cpu and caches 102cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 103 L1(size = '32kB', assoc = 4), 104 L2(size = '4MB', assoc = 8), 105 PageTableWalkerCache(), 106 PageTableWalkerCache()) 107# create the interrupt controller 108cpu.createInterruptController() 109# connect cpu and caches to the rest of the system 110cpu.connectAllPorts(system.membus) 111# set the cpu clock along with the caches and l1-l2 bus 112cpu.clock = '2GHz' 113 114root = Root(full_system=True, system=system) 115m5.ticks.setGlobalFrequency('1THz') 116 | 49system.iocache.cpu_side = system.iobus.master 50system.iocache.mem_side = system.membus.slave 51 52#connect up the cpu and caches 53cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 54 L1(size = '32kB', assoc = 4), 55 L2(size = '4MB', assoc = 8), 56 PageTableWalkerCache(), 57 PageTableWalkerCache()) 58# create the interrupt controller 59cpu.createInterruptController() 60# connect cpu and caches to the rest of the system 61cpu.connectAllPorts(system.membus) 62# set the cpu clock along with the caches and l1-l2 bus 63cpu.clock = '2GHz' 64 65root = Root(full_system=True, system=system) 66m5.ticks.setGlobalFrequency('1THz') 67 |