pc-o3-timing.py (8876:44f8e7bb7fdf) pc-o3-timing.py (8883:c92153af04ac)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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72# ---------------------
73class IOCache(BaseCache):
74 assoc = 8
75 block_size = 64
76 latency = '50ns'
77 mshrs = 20
78 size = '1kB'
79 tgts_per_mshr = 12
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 63 unchanged lines hidden (view full) ---

72# ---------------------
73class IOCache(BaseCache):
74 assoc = 8
75 block_size = 64
76 latency = '50ns'
77 mshrs = 20
78 size = '1kB'
79 tgts_per_mshr = 12
80 addr_range = AddrRange(0, size=mem_size)
80 addr_ranges = [AddrRange(0, size=mem_size)]
81 forward_snoops = False
82
83#cpu
84cpu = DerivO3CPU(cpu_id=0)
85#the system
86mdesc = SysConfig(disk = 'linux-x86.img')
87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
81 forward_snoops = False
82
83#cpu
84cpu = DerivO3CPU(cpu_id=0)
85#the system
86mdesc = SysConfig(disk = 'linux-x86.img')
87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
89system.iocache = IOCache(addr_range=mem_size)
89system.iocache = IOCache()
90system.iocache.cpu_side = system.iobus.master
91system.iocache.mem_side = system.membus.slave
92
93system.cpu = cpu
94#create the l1/l2 bus
95system.toL2Bus = Bus()
96
97#connect up the l2 cache

--- 18 unchanged lines hidden --- 		90system.iocache.cpu_side = system.iobus.master
91system.iocache.mem_side = system.membus.slave
92
93system.cpu = cpu
94#create the l1/l2 bus
95system.toL2Bus = Bus()
96
97#connect up the l2 cache

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