pc-o3-timing.py (8801:1a84c6a81299) pc-o3-timing.py (8839:eeb293859255)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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82
83#cpu
84cpu = DerivO3CPU(cpu_id=0)
85#the system
86mdesc = SysConfig(disk = 'linux-x86.img')
87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
89system.iocache = IOCache(addr_range=mem_size)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 73 unchanged lines hidden (view full) ---

82
83#cpu
84cpu = DerivO3CPU(cpu_id=0)
85#the system
86mdesc = SysConfig(disk = 'linux-x86.img')
87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
89system.iocache = IOCache(addr_range=mem_size)
90system.iocache.cpu_side = system.iobus.port
91system.iocache.mem_side = system.membus.port
90system.iocache.cpu_side = system.iobus.master
91system.iocache.mem_side = system.membus.slave
92
93system.cpu = cpu
94#create the l1/l2 bus
95system.toL2Bus = Bus()
96
97#connect up the l2 cache
98system.l2c = L2(size='4MB', assoc=8)
92
93system.cpu = cpu
94#create the l1/l2 bus
95system.toL2Bus = Bus()
96
97#connect up the l2 cache
98system.l2c = L2(size='4MB', assoc=8)
99system.l2c.cpu_side = system.toL2Bus.port
100system.l2c.mem_side = system.membus.port
99system.l2c.cpu_side = system.toL2Bus.master
100system.l2c.mem_side = system.membus.slave
101
102#connect up the cpu and l1s
103cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
104 L1(size = '32kB', assoc = 4),
105 PageTableWalkerCache(),
106 PageTableWalkerCache())
107# connect cpu level-1 caches to shared level-2 cache
108cpu.connectAllPorts(system.toL2Bus, system.membus)
109cpu.clock = '2GHz'
110
111root = Root(full_system=True, system=system)
112m5.ticks.setGlobalFrequency('1THz')
113
101
102#connect up the cpu and l1s
103cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
104 L1(size = '32kB', assoc = 4),
105 PageTableWalkerCache(),
106 PageTableWalkerCache())
107# connect cpu level-1 caches to shared level-2 cache
108cpu.connectAllPorts(system.toL2Bus, system.membus)
109cpu.clock = '2GHz'
110
111root = Root(full_system=True, system=system)
112m5.ticks.setGlobalFrequency('1THz')
113