| pc-o3-timing.py (8631:8c038d4cd210) | pc-o3-timing.py (8713:2f1a3e335255) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 72 unchanged lines hidden (view full) --- 81 forward_snoops = False 82 83#cpu 84cpu = DerivO3CPU(cpu_id=0) 85#the system 86mdesc = SysConfig(disk = 'linux-x86.img') 87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 72 unchanged lines hidden (view full) --- 81 forward_snoops = False 82 83#cpu 84cpu = DerivO3CPU(cpu_id=0) 85#the system 86mdesc = SysConfig(disk = 'linux-x86.img') 87system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 88system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') |
| 89system.bridge.filter_ranges_a = [AddrRange(0, Addr.max >> 4)] 90system.bridge.filter_ranges_b = [AddrRange(0, size=mem_size)] | |
| 91system.iocache = IOCache(addr_range=mem_size) 92system.iocache.cpu_side = system.iobus.port 93system.iocache.mem_side = system.membus.port 94 95system.cpu = cpu 96#create the l1/l2 bus 97system.toL2Bus = Bus() 98 --- 17 unchanged lines hidden --- | 89system.iocache = IOCache(addr_range=mem_size) 90system.iocache.cpu_side = system.iobus.port 91system.iocache.mem_side = system.membus.port 92 93system.cpu = cpu 94#create the l1/l2 bus 95system.toL2Bus = Bus() 96 --- 17 unchanged lines hidden --- |