1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 94 unchanged lines hidden (view full) --- 103cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 104 L1(size = '32kB', assoc = 4), 105 PageTableWalkerCache(), 106 PageTableWalkerCache()) 107# connect cpu level-1 caches to shared level-2 cache 108cpu.connectAllPorts(system.toL2Bus, system.membus) 109cpu.clock = '2GHz' 110 |
111root = Root(full_system=True, system=system) |
112m5.ticks.setGlobalFrequency('1THz') 113 |