pc-o3-timing.py (9263:066099902102) | pc-o3-timing.py (9282:ac627fdc8991) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 76 unchanged lines hidden (view full) --- 85 forward_snoops = False 86 87#cpu 88cpu = DerivO3CPU(cpu_id=0) 89#the system 90mdesc = SysConfig(disk = 'linux-x86.img') 91system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 92system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 76 unchanged lines hidden (view full) --- 85 forward_snoops = False 86 87#cpu 88cpu = DerivO3CPU(cpu_id=0) 89#the system 90mdesc = SysConfig(disk = 'linux-x86.img') 91system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) 92system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') |
93 94system.cpu = cpu 95 96#create the iocache |
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93system.iocache = IOCache() 94system.iocache.cpu_side = system.iobus.master 95system.iocache.mem_side = system.membus.slave 96 | 97system.iocache = IOCache() 98system.iocache.cpu_side = system.iobus.master 99system.iocache.mem_side = system.membus.slave 100 |
97system.cpu = cpu 98#create the l1/l2 bus 99system.toL2Bus = CoherentBus() 100 101#connect up the l2 cache 102system.l2c = L2(size='4MB', assoc=8) 103system.l2c.cpu_side = system.toL2Bus.master 104system.l2c.mem_side = system.membus.slave 105 106#connect up the cpu and l1s 107cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 108 L1(size = '32kB', assoc = 4), 109 PageTableWalkerCache(), 110 PageTableWalkerCache()) | 101#connect up the cpu and caches 102cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), 103 L1(size = '32kB', assoc = 4), 104 L2(size = '4MB', assoc = 8), 105 PageTableWalkerCache(), 106 PageTableWalkerCache()) |
111# create the interrupt controller 112cpu.createInterruptController() | 107# create the interrupt controller 108cpu.createInterruptController() |
113# connect cpu level-1 caches to shared level-2 cache 114cpu.connectAllPorts(system.toL2Bus, system.membus) | 109# connect cpu and caches to the rest of the system 110cpu.connectAllPorts(system.membus) 111# set the cpu clock along with the caches and l1-l2 bus |
115cpu.clock = '2GHz' 116 117root = Root(full_system=True, system=system) 118m5.ticks.setGlobalFrequency('1THz') 119 | 112cpu.clock = '2GHz' 113 114root = Root(full_system=True, system=system) 115m5.ticks.setGlobalFrequency('1THz') 116 |