| o3-timing.py (9792:c02004c2cc5b) | o3-timing.py (10406:3819b85ff21a) |
|---|---|
| 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 25 unchanged lines hidden (view full) --- 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40 41from m5.objects import * | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 25 unchanged lines hidden (view full) --- 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40 41from m5.objects import * |
| 42from m5.defines import buildEnv |
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| 42from base_config import * | 43from base_config import * |
| 44from arm_generic import * 45from O3_ARM_v7a import O3_ARM_v7a_3 |
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| 43 | 46 |
| 44root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, 45 cpu_class=DerivO3CPU).create_root() | 47# If we are running ARM regressions, use a more sensible CPU 48# configuration. This makes the results more meaningful, and also 49# increases the coverage of the regressions. 50if buildEnv['TARGET_ISA'] == "arm": 51 root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, 52 cpu_class=O3_ARM_v7a_3).create_root() 53else: 54 root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, 55 cpu_class=DerivO3CPU).create_root() |