o3-timing.py (9381:ffec48040ac1) | o3-timing.py (9489:172dbcb74a0e) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 L1Cache(size = '256kB'), 37 L2Cache(size = '2MB')) 38# @todo Note that the L2 latency here is unmodified and 2 cycles, 39# should set hit latency and response latency to 20 cycles as for 40# other scripts 41cpu.clock = '2GHz' 42 43system = System(cpu = cpu, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 L1Cache(size = '256kB'), 37 L2Cache(size = '2MB')) 38# @todo Note that the L2 latency here is unmodified and 2 cycles, 39# should set hit latency and response latency to 20 cycles as for 40# other scripts 41cpu.clock = '2GHz' 42 43system = System(cpu = cpu, |
44 physmem = SimpleDRAM(), | 44 physmem = SimpleDDR3(), |
45 membus = CoherentBus(), 46 mem_mode = "timing") 47system.system_port = system.membus.slave 48system.physmem.port = system.membus.master 49# create the interrupt controller 50cpu.createInterruptController() 51cpu.connectAllPorts(system.membus) 52 53root = Root(full_system = False, system = system) | 45 membus = CoherentBus(), 46 mem_mode = "timing") 47system.system_port = system.membus.slave 48system.physmem.port = system.membus.master 49# create the interrupt controller 50cpu.createInterruptController() 51cpu.connectAllPorts(system.membus) 52 53root = Root(full_system = False, system = system) |