| o3-timing.py (9311:227d19399b51) | o3-timing.py (9321:7f0464326b2b) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 15 unchanged lines hidden (view full) --- 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 15 unchanged lines hidden (view full) --- 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') |
| 32from Caches import * |
|
| 32 | 33 |
| 33class MyCache(BaseCache): 34 assoc = 2 35 block_size = 64 36 hit_latency = 2 37 response_latency = 2 38 mshrs = 10 39 tgts_per_mshr = 5 40 41class MyL1Cache(MyCache): 42 is_top_level = True 43 tgts_per_mshr = 20 44 | |
| 45cpu = DerivO3CPU(cpu_id=0) | 34cpu = DerivO3CPU(cpu_id=0) |
| 46cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 47 MyL1Cache(size = '256kB'), 48 MyCache(size = '2MB')) | 35cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'), 36 L1Cache(size = '256kB'), 37 L2Cache(size = '2MB')) |
| 49# @todo Note that the L2 latency here is unmodified and 2 cycles, 50# should set hit latency and response latency to 20 cycles as for 51# other scripts 52cpu.clock = '2GHz' 53 54system = System(cpu = cpu, 55 physmem = SimpleDRAM(), 56 membus = CoherentBus()) 57system.system_port = system.membus.slave 58system.physmem.port = system.membus.master 59# create the interrupt controller 60cpu.createInterruptController() 61cpu.connectAllPorts(system.membus) 62 63root = Root(full_system = False, system = system) | 38# @todo Note that the L2 latency here is unmodified and 2 cycles, 39# should set hit latency and response latency to 20 cycles as for 40# other scripts 41cpu.clock = '2GHz' 42 43system = System(cpu = cpu, 44 physmem = SimpleDRAM(), 45 membus = CoherentBus()) 46system.system_port = system.membus.slave 47system.physmem.port = system.membus.master 48# create the interrupt controller 49cpu.createInterruptController() 50cpu.connectAllPorts(system.membus) 51 52root = Root(full_system = False, system = system) |