| o3-timing.py (9288:3d6da8559605) | o3-timing.py (9311:227d19399b51) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 38 unchanged lines hidden (view full) --- 47 MyL1Cache(size = '256kB'), 48 MyCache(size = '2MB')) 49# @todo Note that the L2 latency here is unmodified and 2 cycles, 50# should set hit latency and response latency to 20 cycles as for 51# other scripts 52cpu.clock = '2GHz' 53 54system = System(cpu = cpu, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 38 unchanged lines hidden (view full) --- 47 MyL1Cache(size = '256kB'), 48 MyCache(size = '2MB')) 49# @todo Note that the L2 latency here is unmodified and 2 cycles, 50# should set hit latency and response latency to 20 cycles as for 51# other scripts 52cpu.clock = '2GHz' 53 54system = System(cpu = cpu, |
| 55 physmem = SimpleMemory(), | 55 physmem = SimpleDRAM(), |
| 56 membus = CoherentBus()) 57system.system_port = system.membus.slave 58system.physmem.port = system.membus.master 59# create the interrupt controller 60cpu.createInterruptController() 61cpu.connectAllPorts(system.membus) 62 63root = Root(full_system = False, system = system) | 56 membus = CoherentBus()) 57system.system_port = system.membus.slave 58system.physmem.port = system.membus.master 59# create the interrupt controller 60cpu.createInterruptController() 61cpu.connectAllPorts(system.membus) 62 63root = Root(full_system = False, system = system) |