o3-timing.py (9036:6385cf85bf12) o3-timing.py (9263:066099902102)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32
33class MyCache(BaseCache):
34 assoc = 2
35 block_size = 64
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 19 unchanged lines hidden (view full) ---

28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32
33class MyCache(BaseCache):
34 assoc = 2
35 block_size = 64
36 latency = '1ns'
36 hit_latency = '1ns'
37 response_latency = '1ns'
37 mshrs = 10
38 tgts_per_mshr = 5
39
40class MyL1Cache(MyCache):
41 is_top_level = True
42 tgts_per_mshr = 20
43
44cpu = DerivO3CPU(cpu_id=0)

--- 15 unchanged lines hidden --- 		38 mshrs = 10
39 tgts_per_mshr = 5
40
41class MyL1Cache(MyCache):
42 is_top_level = True
43 tgts_per_mshr = 20
44
45cpu = DerivO3CPU(cpu_id=0)

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