| o3-timing.py (8931:7a1dfb191e3f) | o3-timing.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 35 unchanged lines hidden (view full) --- 44cpu = DerivO3CPU(cpu_id=0) 45cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 46 MyL1Cache(size = '256kB'), 47 MyCache(size = '2MB')) 48cpu.clock = '2GHz' 49 50system = System(cpu = cpu, 51 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 35 unchanged lines hidden (view full) --- 44cpu = DerivO3CPU(cpu_id=0) 45cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), 46 MyL1Cache(size = '256kB'), 47 MyCache(size = '2MB')) 48cpu.clock = '2GHz' 49 50system = System(cpu = cpu, 51 physmem = SimpleMemory(), |
| 52 membus = Bus()) | 52 membus = CoherentBus()) |
| 53system.system_port = system.membus.slave 54system.physmem.port = system.membus.master 55# create the interrupt controller 56cpu.createInterruptController() 57cpu.connectAllPorts(system.membus) 58 59root = Root(full_system = False, system = system) | 53system.system_port = system.membus.slave 54system.physmem.port = system.membus.master 55# create the interrupt controller 56cpu.createInterruptController() 57cpu.connectAllPorts(system.membus) 58 59root = Root(full_system = False, system = system) |