| o3-timing.py (8839:eeb293859255) | o3-timing.py (8876:44f8e7bb7fdf) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 38 unchanged lines hidden (view full) --- 47 MyCache(size = '2MB')) 48cpu.clock = '2GHz' 49 50system = System(cpu = cpu, 51 physmem = PhysicalMemory(), 52 membus = Bus()) 53system.system_port = system.membus.slave 54system.physmem.port = system.membus.master | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 38 unchanged lines hidden (view full) --- 47 MyCache(size = '2MB')) 48cpu.clock = '2GHz' 49 50system = System(cpu = cpu, 51 physmem = PhysicalMemory(), 52 membus = Bus()) 53system.system_port = system.membus.slave 54system.physmem.port = system.membus.master |
| 55# create the interrupt controller 56cpu.createInterruptController() |
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| 55cpu.connectAllPorts(system.membus) 56 57root = Root(full_system = False, system = system) | 57cpu.connectAllPorts(system.membus) 58 59root = Root(full_system = False, system = system) |