| o3-timing.py (6654:4c84e771cca7) | o3-timing.py (7876:189b9b258779) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 42 MyCache(size = '2MB')) 43cpu.clock = '2GHz' 44 45system = System(cpu = cpu, 46 physmem = PhysicalMemory(), 47 membus = Bus()) 48system.physmem.port = system.membus.port | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 32 unchanged lines hidden (view full) --- 41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 42 MyCache(size = '2MB')) 43cpu.clock = '2GHz' 44 45system = System(cpu = cpu, 46 physmem = PhysicalMemory(), 47 membus = Bus()) 48system.physmem.port = system.membus.port |
| 49cpu.connectMemPorts(system.membus) | 49cpu.connectAllPorts(system.membus) |
| 50 51root = Root(system = system) | 50 51root = Root(system = system) |