o3-timing.py (4390:76bbcf725852) | o3-timing.py (4444:0648bdc8d1c9) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29import m5 30from m5.objects import * 31m5.AddToPath('../configs/common') 32 33class MyCache(BaseCache): 34 assoc = 2 35 block_size = 64 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29import m5 30from m5.objects import * 31m5.AddToPath('../configs/common') 32 33class MyCache(BaseCache): 34 assoc = 2 35 block_size = 64 |
36 latency = 1 | 36 latency = '1ns' |
37 mshrs = 10 38 tgts_per_mshr = 5 39 40cpu = DerivO3CPU(cpu_id=0) 41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 42 MyCache(size = '2MB')) 43cpu.clock = '2GHz' 44 45system = System(cpu = cpu, 46 physmem = PhysicalMemory(), 47 membus = Bus()) 48system.physmem.port = system.membus.port 49cpu.connectMemPorts(system.membus) 50 51root = Root(system = system) | 37 mshrs = 10 38 tgts_per_mshr = 5 39 40cpu = DerivO3CPU(cpu_id=0) 41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 42 MyCache(size = '2MB')) 43cpu.clock = '2GHz' 44 45system = System(cpu = cpu, 46 physmem = PhysicalMemory(), 47 membus = Bus()) 48system.physmem.port = system.membus.port 49cpu.connectMemPorts(system.membus) 50 51root = Root(system = system) |