o3-timing.py (3223:a2b6fa575c05) o3-timing.py (3402:db60546818d0)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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35 block_size = 64
36 latency = 1
37 mshrs = 10
38 tgts_per_mshr = 5
39
40cpu = DerivO3CPU()
41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
42 MyCache(size = '2MB'))
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 26 unchanged lines hidden (view full) ---

35 block_size = 64
36 latency = 1
37 mshrs = 10
38 tgts_per_mshr = 5
39
40cpu = DerivO3CPU()
41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
42 MyCache(size = '2MB'))
43cpu.mem = cpu.dcache
44
45system = System(cpu = cpu,
46 physmem = PhysicalMemory(),
47 membus = Bus())
48system.physmem.port = system.membus.port
49cpu.connectMemPorts(system.membus)
50
51root = Root(system = system)
43
44system = System(cpu = cpu,
45 physmem = PhysicalMemory(),
46 membus = Bus())
47system.physmem.port = system.membus.port
48cpu.connectMemPorts(system.membus)
49
50root = Root(system = system)