o3-timing.py (3096:f621bee6e8df) o3-timing.py (3223:a2b6fa575c05)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32from FullO3Config import *
33
34class MyCache(BaseCache):
35 assoc = 2
36 block_size = 64
37 latency = 1
38 mshrs = 10
39 tgts_per_mshr = 5
40
32
33class MyCache(BaseCache):
34 assoc = 2
35 block_size = 64
36 latency = 1
37 mshrs = 10
38 tgts_per_mshr = 5
39
41cpu = DetailedO3CPU()
40cpu = DerivO3CPU()
42cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
43 MyCache(size = '2MB'))
44cpu.mem = cpu.dcache
45
46system = System(cpu = cpu,
47 physmem = PhysicalMemory(),
48 membus = Bus())
49system.physmem.port = system.membus.port
50cpu.connectMemPorts(system.membus)
51
52root = Root(system = system)
41cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
42 MyCache(size = '2MB'))
43cpu.mem = cpu.dcache
44
45system = System(cpu = cpu,
46 physmem = PhysicalMemory(),
47 membus = Bus())
48system.physmem.port = system.membus.port
49cpu.connectMemPorts(system.membus)
50
51root = Root(system = system)